GICP_PMU_IRQ_TRIGGER (LPD_SLCR) Register Description
| Register Name | GICP_PMU_IRQ_TRIGGER |
|---|---|
| Offset Address | 0x00000080B0 |
| Absolute Address | 0x00FF4180B0 (LPD_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Trigger Register. A write of one to this location will set the interrupt status register related to this interrupt. |
GICP_PMU_IRQ_TRIGGER (LPD_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | razRead as zero | 0x0 | Reserved for future use |
| src4 | 4 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP4 |
| src3 | 3 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP3 |
| src2 | 2 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP2 |
| src1 | 1 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP1 |
| src0 | 0 | woWrite-only | 0x0 | Create single interrupt source for PMU from GICP0 |