GDMAHLRATIO (USB3_XHCI) Register Description
| Register Name | GDMAHLRATIO |
|---|---|
| Offset Address | 0x000000C624 |
| Absolute Address |
0x00FE20C624 (USB3_0_XHCI) 0x00FE30C624 (USB3_1_XHCI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Global Host FIFO DMA High-Low Priority Ratio Register This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low Priority Ratio grants as indicated in the register separately for TX and RX. To illustrate, consider that all FIFOs are requesting access simultaneously, and the ratio is 4. SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, SS gets priority for 4 packets, HS/FSLS gets priority for 1 packet, and so on. If FIFOs from both speed groups are not requesting access simultaneously then, - if SS got grants 4 out of the last 4 times, then HS/FSLS get the priority on any future request. - if HS/FSLS got the grant last time, SS gets the priority on the next request. - if there is a valid request on either SS or HS/FSLS, a grant is always awarded; there is no idle. This register is present if the core is configured to operate in host mode (includes DRD and OTG). |
GDMAHLRATIO (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:13 | roRead-only | 0x0 | Reserved |
| hstrxfifo | 12:8 | rwNormal read/write | 0 | Host RXFIFO DMA High-Low Priority |
| Reserved | 7:5 | roRead-only | 0x0 | Reserved |
| hsttxfifo | 4:0 | rwNormal read/write | 0 | Host TXFIFO DMA High-Low Priority |