Event_Control_Timer_2 (TTC) Register Description
| Register Name | Event_Control_Timer_2 |
|---|---|
| Offset Address | 0x0000000070 |
| Absolute Address |
0x00FF110070 (TTC0) 0x00FF120070 (TTC1) 0x00FF130070 (TTC2) 0x00FF140070 (TTC3) |
| Width | 4 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Enable, pulse and overflow |
Event_Control_Timer_2 (TTC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| E_TM | 3 | rwNormal read/write | 0x0 | Test Mode: when this bit is high, the event timer is pre-loaded with 0xFFFF0000 and will overflow to this value if set to do so. |
| E_Ov | 2 | rwNormal read/write | 0x0 | When this bit is low, the event timer is disabled and set to zero when an Event Timer Register overflow occurs; when set high, the timer continues counting on overflow. |
| E_Lo | 1 | rwNormal read/write | 0x0 | When this bit is high, the timer counts LPD_LSBUS_CLK clock cycles during the low level duration of ext_clk; when low, the event timer counts the high level duration of ext_clk. |
| E_En | 0 | rwNormal read/write | 0x0 | Enable timer: when this bit is high, the event timer is enabled. |