ERR_STATUS2 (XMPU_DDR) Register Description
| Register Name | ERR_STATUS2 |
|---|---|
| Offset Address | 0x0000000008 |
| Absolute Address |
0x00FD000008 (DDR_XMPU0_CFG) 0x00FD010008 (DDR_XMPU1_CFG) 0x00FD020008 (DDR_XMPU2_CFG) 0x00FD030008 (DDR_XMPU3_CFG) 0x00FD040008 (DDR_XMPU4_CFG) 0x00FD050008 (DDR_XMPU5_CFG) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Error Status, Reg 2. |
The first AXI violation is recorded. Once a violation status flag is set in the ISR register, subsequent violations are not recorded. This register is reset by clearing a violation flag in the ISR register.
ERR_STATUS2 (XMPU_DDR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:10 | roRead-only | 0x0 | reserved |
| AXI_ID | 9:0 | roRead-only | 0x0 | Master ID from a poisoned read or write transaction. Read-only. |