ERR_AIBAPB_IMR (LPD_SLCR) Register Description
| Register Name | ERR_AIBAPB_IMR |
|---|---|
| Offset Address | 0x0000003024 |
| Absolute Address | 0x00FF413024 (LPD_SLCR) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000001 |
| Description | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
ERR_AIBAPB_IMR (LPD_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | roRead-only | 0x0 | reserved |
| Reserved | 3 | roRead-only | 0x0 | reserved |
| Reserved | 2 | roRead-only | 0x0 | reserved |
| Reserved | 1 | roRead-only | 0x0 | reserved |
| gpu | 0 | roRead-only | 0x1 | AIB_APB for GPU |