EP_CTRL (PCIE_ATTRIB) Register Description
| Register Name | EP_CTRL |
|---|---|
| Offset Address | 0x0000000230 |
| Absolute Address | 0x00FD480230 (PCIE_ATTRIB) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | PL End Point Mode Control Register |
EP_CTRL (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| pl_upstream_deemph_source | 1 | rwNormal read/write | 0x0 | Enables the Endpoint to control de-emphasis used on the link at 5.0 Gb/s speeds. 0b - -6 dB de-emphasis recommended for short, reflection dominated channels. 1b - -3.5 dB de-emphasis recommended for long, loss dominated channels. |
| pl_received_hot_rst | 0 | roRead-only | 0x0 | Indicates In-Band Hot Reset has been received |