DPLL_CTRL (CRF_APB) Register Description
| Register Name | DPLL_CTRL |
|---|---|
| Offset Address | 0x000000002C |
| Absolute Address | 0x00FD1A002C (CRF_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00002C09 |
| Description | DPLL Clock Unit Control |
DPLL_CTRL (CRF_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| POST_SRC | 26:24 | rwNormal read/write | 0x0 | Select the pass-thru clock source for PLL Bypass mode. 0xx: PS_REF_CLK 100: VIDEO_REF_CLK 101: ALT_REF_CLK 110: AUX_REF_CLK 111: GT_REF_CLK |
| PRE_SRC | 22:20 | rwNormal read/write | 0x0 | Select the clock source for PLL input. 0xx: PS_REF_CLK 100: VIDEO_REF_CLK 101: ALT_REF_CLK 110: AUX_REF_CLK 111: GT_REF_CLK |
| DIV2 | 16 | rwNormal read/write | 0x0 | Enable the divide by 2 function inside of the PLL. 0: no effect. 1: divide clock by 2. Note: this does not change the VCO frequency, just the output frequency. |
| FBDIV | 14:8 | rwNormal read/write | 0x2C | Feedback divisor integer portion for the PLL. |
| BYPASS | 3 | rwNormal read/write | 0x1 | PLL Clock Bypass Mode. 0: normal PLL mode; the source clock is selected using [PRE_SRC]. 1: bypass the PLL; the source clock is selected using [POST_SRC]. |
| RESET | 0 | rwNormal read/write | 0x1 | PLL reset. 0: active. 1: reset. Note: Program the PLL into bypass mode before resetting the PLL. |