DPDMA_ALC1_CNTL (DPDMA) Register Description
| Register Name | DPDMA_ALC1_CNTL |
|---|---|
| Offset Address | 0x0000000120 |
| Absolute Address | 0x00FD4C0120 (DPDMA) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Global control register provides control to start or redirect any channel |
DPDMA_ALC1_CNTL (DPDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:6 | razRead as zero | 0x0 | Reseved for future use |
| MON_ID | 5:2 | rwNormal read/write | 0x0 | ALC uses this ID to filter the traffic on AXI channel and calculates latency number |
| CLEAR | 1 | woWrite-only | 0x0 | this bit will clear the state of ALC |
| EN | 0 | rwNormal read/write | 0x0 | Enable bit for ALC1 1: ALC is enable, it is calculating Min , Max and Ave 0: ALC is disable, it preserves the previous state untill "ALC Clear |