DMA_CHANNEL_DST_Q_SIZE (AXIPCIE_DMA) Register Description
| Register Name | DMA_CHANNEL_DST_Q_SIZE |
|---|---|
| Offset Address | 0x0000000018 |
| Absolute Address |
0x00FD0F0018 (AXIPCIE_DMA0) 0x00FD0F0098 (AXIPCIE_DMA1) 0x00FD0F0118 (AXIPCIE_DMA2) 0x00FD0F0198 (AXIPCIE_DMA3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Queue Size |
DMA_CHANNEL_DST_Q_SIZE (AXIPCIE_DMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| queue_size | 31:0 | rwNormal read/write | 0x0 | Queue Size. Number of Elements in the Queue. queue_size must be >= 2. A minimum of 2 elements is required to support software/hardware queue flow control ownership. queue_size is used to identify the wrap boundary of the Queue. |