Config_reg (QSPI) Register Description
| Register Name | Config_reg |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FF0F0000 (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x80000000 |
| Description | QSPI configuration register |
Note: Change this value only when controller is not communicating with the memory device. Software Driver name: XQSPIPS_CR
Config_reg (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| leg_flsh | 31 | rwNormal read/write | 0x1 | Flash memory interface mode control: 1: Flash memory interface mode 0: legacy SPI mode This control is required to enable or disable automatic recognition of instruction bytes in the first byte of a transfer. If this mode is disabled, the core will operate in standard SPI mode, with no dual- or quad-bit input or output capability; the extended bits will be configured as inputs to prevent any driver contention on these pins. If enabled, flash memory interface instructions are automatically recognized and the I/O configured accordingly. Software Driver name: XQSPIPS_CR_IFMODE |
| Reserved | 30:27 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| endian | 26 | rwNormal read/write | 0x0 | 0: little endian format when writing to the transmit data register 0x1C or reading from the receive data register 0x20. 1: big endian format when writing to the transmit data register 0x1C or reading from the receive data register 0x20. Software Driver name: XQSPIPS_CR_ENDIAN |
| Reserved | 25:20 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| Holdb_dr | 19 | rwNormal read/write | 0x0 | If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes. If not set, then external pull up is required on HOLDb and WPn pins. Note that this bit doesn't affect the quad (4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI. |
| Reserved | 18:17 | rwNormal read/write | 0x0 | Reserved |
| Man_start_com | 16 | woWrite-only | 0x0 | Manual Start Command Software Driver name: XQSPIPS_CR_MANSTRT 0: don't care 1: start transmission of data |
| Man_start_en | 15 | rwNormal read/write | 0x0 | Manual Start Enable Software Driver name: XQSPIPS_CR_MANSTRTEN 0: auto mode 1: enables manual start |
| Manual_CS | 14 | rwNormal read/write | 0x0 | Manual CS Software Driver name: XQSPIPS_CR_SSFORCE 0: auto mode 1: manual CS mode |
| Reserved | 13:11 | rwNormal read/write | 0x0 | Reserved |
| PCS | 10 | rwNormal read/write | 0x0 | Peripheral chip select line, directly drive n_ss_out if Manual_CS is set. In manual CS mode, this bit should be programmed before writing Transmit Data Registers (TXDx). |
| Reserved | 9 | rwNormal read/write | 0x0 | Reserved |
| REF_CLK | 8 | rwNormal read/write | 0x0 | Reserved. Must be 0 |
| FIFO_WIDTH | 7:6 | rwNormal read/write | 0x0 | FIFO width Must be set to 2b11 (32bits). All other settings are not supported. |
| BAUD_RATE_DIV | 5:3 | rwNormal read/write | 0x0 | Master mode baud rate divisor 000: divide by 2. This is the only baud rate setting that can be used if the loopback clock is enabled [USE_LPBK]. 001: divide by 4 010: divide by 8 011: divide by 16 100: divide by 32 101: divide by 64 110: divide by 128 111: divide by 256 |
| CLK_PH | 2 | rwNormal read/write | 0x0 | Clock phase Software Driver name: XQSPIPS_CR_CPHA 0: QSPI clock is active outside the word 1: QSPI clock is inactive outside the word Note: For {CLK_PH, CLK_POL}, only 2b11 and 2b00 are supported. |
| CLK_POL | 1 | rwNormal read/write | 0x0 | Clock polarity outside QSPI word Software Driver name: XQSPIPS_CR_CPOL 0: QSPI clock is quiescent low 1: QSPI clock is quiescent high Note: For {CLK_PH, CLK_POL}, only 2b11 and 2b00 are supported. |
| MODE_SEL | 0 | rwNormal read/write | 0x0 | Mode select Software Driver name: XQSPIPS_CR_MSTREN 0: reserved 1: QSPI is in master mode In QSPI boot mode, ROM code will set this bit. In other boot modes, this bit must be set before using QSPI. |