CONTROL (AFIFM) Register Description
| Register Name | CONTROL |
|---|---|
| Offset Address | 0x0000000F04 |
| Absolute Address |
0x00FD360F04 (AFIFM0) 0x00FD370F04 (AFIFM1) 0x00FD380F04 (AFIFM2) 0x00FD390F04 (AFIFM3) 0x00FD3A0F04 (AFIFM4) 0x00FD3B0F04 (AFIFM5) 0x00FF9B0F04 (AFIFM6) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | General Control Register |
General Control fields that affect Both Read and Write Channels
CONTROL (AFIFM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. |
| APB_ERR_RESP | 0 | rwNormal read/write | 0x0 | When an APB (register) access occurs to an unimplemented space (there is no register at that location), the resulting pslverr will be: 0: pslverr = 1b0 1: pslverr = 1b1 Software Driver name: XQSPIPS_IXR_RXNEMPTY |