CIDR0 (A53_PMU_0) Register Description
| Register Name | CIDR0 |
|---|---|
| Offset Address | 0x0000000FF0 |
| Absolute Address | 0x00FEC30FF0 (CORESIGHT_A53_PMU_0) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x0000000D |
| Description | Performance Monitors Component Identification Register 0 |
CIDR0 (A53_PMU_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PRMBL_0 | 7:0 | roRead-only | 0xD | Preamble. Must read as 0x0D. |