CIDCVR0 (A53_ETM_1) Register Description
| Register Name | CIDCVR0 |
|---|---|
| Offset Address | 0x0000000600 |
| Absolute Address | 0x00FED40600 (CORESIGHT_A53_ETM_1) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Context ID Comparator Value Register 0 |
CIDCVR0 (A53_ETM_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| VALUE | 31:0 | rwNormal read/write | 0 | Context ID value. The implemented width of this field is IMPLEMENTATION DEFINED and is set by IDR2.CIDSIZE. Unimplemented bits are RAZ/WI.After a processor reset, the ETM architecture assumes that the Context ID is zero until the processor updates the Context ID. |