CHKR7_CTRL (CRL_APB) Register Description
| Register Name | CHKR7_CTRL |
|---|---|
| Offset Address | 0x00000001DC |
| Absolute Address | 0x00FF5E01DC (CRL_APB) |
| Width | 9 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Clock Checker 7 Control. |
CHKR7_CTRL (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| start_single | 8 | rwNormal read/write | 0x0 | Start checking mechanism once. 0: no effect. 1: check the clock once (self clearing to 0). The start bit must be asserted after all other control bits are set. |
| start_continuous | 7 | rwNormal read/write | 0x0 | Start the checking mechanism and keep checking until bit is set back to zero. 0: single check. (or stop checking) 1: continous clock checking. The start bit must be asserted after all other control bits are set. |
| Reserved | 6 | rwNormal read/write | 0x0 | reserved |
| clkb_mux_ctrl | 5 | rwNormal read/write | 0x0 | 0: PS_REF_CLK 1: SYSOSC_CLK |
| Reserved | 4 | rwNormal read/write | 0x0 | reserved |
| clka_mux_ctrl | 3:1 | rwNormal read/write | 0x0 | 000: RPU clock. 001: OCM clock. 010: LPD_SWITCH_CLK clock. 011: LPD_LSBUS_CLK clock. 100: PMU clock. 101: CSU_PLL_CLK clock. 110: SYSOSC_CLK clock. 111: PS_REF_CLK clock. |
| Enable | 0 | rwNormal read/write | 0x0 | This enables the checker, but does not start it. |