Tiling Parameters and Buffer Descriptors - 2025.2 English

Tiling Parameters and Buffer Descriptors - 2025.2 English - UG1079

AI Engine Kernel and Graph Programming Guide (UG1079)

Document ID

UG1079

Release Date

2025-11-26

Version

2025.2 English

Buffer descriptors located in AI Engine memory manage DMA transfers.

These buffer descriptors handle 1D and 2D memory addressing, multiple iterations, lock ID, and buffer descriptor chaining.

Buffer descriptors address generation can be complex and challenging to maintain over time. Hence, the AI Engine compiler supports higher-level address generation when you create and configure tiling parameter objects in the graph. Data transfer is based on the configuration settings of the tiling parameter object associated with the memory. Data transfers occur on a tile basis, that can be as small as a 1x1 element. These are regularly extracted from or written to a memory space. The structure tiling_parameters is defined as follows:

struct tiling_parameters
{
  std::vector<uint32_t> buffer_dimension;
  std::vector<uint32_t> tiling_dimension;
  std::vector<int32_t> offset;
  std::vector<traversing_parameters> tile_traversal;
  int packet_port_id = -1;
  std::vector<uint32_t> boundary_dimension;
};

The members of this structure are:

buffer_dimension: Buffer dimensions in the memory element type (for example, AI Engine memory). buffer_dimension[0] is contiguous in memory and has the fastest access. If you do not specify this member, the dimensions of the associated memory object are used. The AI Engine memory can access data in the first and second dimensions.
tiling_dimension: Tiling dimensions of the data transfer in buffer. The tiling dimension of AI Engine memory can access data in the first and second dimensions.
offset: Multidimensional offset with respect to the starting element in the buffer, assuming the buffer dimension is specified.
tile_traversal: Vector of traversing_parameters.tile_traversal[i] represents the i-th loop of inter-tile traversal, where i=0 represents most inner loop and i=N-1 represents most outer loop. tile_traversal structure is detailed the section below.
packet_port_id: Multiple connections can go through a single port that are previously merged through a pktmerge block or split afterward with a pktsplit block. This member represents the output port ID of the connected pktsplit or the input port ID of the connected pktmerge. If this member is set to a specific id, the data transfer only occurs if the incoming or outgoing data block ID matches this ID.

boundary_dimension: Real data boundary dimension.

The tile_traversal vector is a a key member of the tiling parameter. It describes buffer access. The structure traversing_parameters is as follows:

struct traversing_parameters
{
  uint32_t dimension;
  uint32_t stride;
  uint32_t wrap;
};

The members of this structure are as follows:

dimension: The buffer dimension on which this traversing loop applies. It can be the 0 or first dimension. The stride and wrap members of this structure are applied in the specified dimension.
stride: Represents the distance in terms of buffer element data type between consecutive inter-tile traversal in this dimension.
wrap: Number of tiles to access in this dimension.

When the stride value is lower than the tile size in one or more dimensions, the tiles overlap naturally in that dimension.

Important: All generated addresses are 32-bit aligned. The requirements for accessing data that is less than or equal to 16 bits are as follows:

16-bit data: access as pairs.
8-bit data: access as fours.
4-bit data: access as eights.