This constrains a port (thatis, the port buffer) location to be on the same tile as that of one or more kernels. This ensures that other kernels can access the data buffer without requiring a DMA.
Syntax
"colocated_nodes": [<node list>]
<node list> ::= <node name>[,<node name>...]
<node name> ::= string
Example
{
"PortConstraints": {
"mygraph.k1.in[0]": {
"colocated_nodes": ["mygraph.k1"]
},
"mygraph.k2.in[0]": {
"colocated_nodes": ["mygraph.k2"]
}
}
}