AI Engine to PL Interface Performance - AI Engine to PL Interface Performance - 2026.1 English - UG1079

Versal AI Core Series devices include an AI Engine array with the following column categories.

PL column

Provides PL stream access. Each column supports the following:

• Eight 64-bit slave channels for streaming data into the AI Engine
• Six 64-bit master channels for streaming data to the PL

NoC column

Provides connectivity between the AI Engine array and the NoC. These interfaces can also connect to the PL.

To instruct the AI Engine compiler to select higher frequency interfaces, use the --pl-freq=<number> to specify the clock frequency (in MHz) for the PL kernels. The default value is one quarter of the AI Engine frequency and the maximum supported value is half of the AI Engine frequency. The values depend on the speed grade. Following are examples:

• Option to enable an AI Engine to PL frequency of 300 MHz for all AI Engine to PL interfaces:

  --pl-freq=300

• To set a different frequency for a specific PLIO interface use the following code to set it in the ADF graph.

  adf::PLIO *<input>= new adf::PLIO(<logical_name>, <plio_width>, <file>, <FreqMHz>);

The AI Engine to PL AXI4-Stream channels use boundary logic interface (BLI) connections. These connections include optional BLI registers with the exception of the slave channels 3 and 7. Slave channels 3 and 7 have slower interfaces. Data transfer performance between the AI Engine and PL depends on whether you enable optional BLI registers.

You can use all eight channels without BLI registers for less timing-critical designs. You can still meet PL timing in this case.

For higher frequency designs, you can use only the six fast channels (0,1,2,4,5,6). In these cases, you must register the timing paths from the PL using the BLI registers.

To control the use of BLI registers across the AI Engine to PL channels, use the --pl-register-threshold=<number> compiler option, specified in MHz. The default value is 1/8 of the AI Engine frequency based on speed grade. Following is an example:

• –pl-register-threshold=125

  If the AI Engine to PL frequency exceeds the set threshold (125 MHz in this case), the compiler maps the PLIO interface to high-speed channels with BLI registers enabled. If the PLIO interface frequency does not exceed the pl-register-threshold value, then the compiler uses any of the AI Engine to PL channels.

In summary:

• If pl-freq < pl-register-threshold all eight channels can be used unregistered.
• If pl-freq > pl-register-threshold only the six fast channels can be used, with registering.

pl-register-threshold is a way to control the threshold frequency beyond which only fast channels can be used (with registering).