The AI Engine array interface contains modules to communicate between AI Engines and PL kernels using AXI4-Stream connections. Generally, PL interfaces produce or consume data through stream interfaces. Depending on whether buffer or stream data is communicated by the AI Engine kernels, DMA and ping-pong buffers can be involved.
Note: PL kernels run at a lower frequency than AI Engine kernels. Data must
cross the clock domains between the AI Engine
clock and PL clock. The AMD Vitis™
environment handles
the clock domain crossing (CDC) path automatically.
It
is recommended to run the PL kernel frequency as an integer factor of the AI Engine frequency, if possible. For example, as ½ or
¼ of the AI Engine clock frequency.