For stream switch FIFO visualization, in the IDE, select the Graph view and select the stream switch FIFO in the view.
Tip: Hover the mouse on the stream
switch FIFO to show information about the FIFO location.
The following figure shows an example of DMA FIFO in Graph view:
Figure 1. Stream Switch FIFO in the Graph View
The Trace view also highlights the selected stream switch FIFO.
The timeline shows the DMA FIFO size in words (see the following figure). The
Events view shows size
information for the DMA_FIFO_SIZE event.
Figure 2. Stream Switch FIFO in the Trace View
Note: Trace view does not display all FIFOs when multiple
stream switch FIFOs are chained. Trace view only shows those with a FIFO size
greater than one.
You can use stream switch FIFO information together with other design analyzing techniques to help design optimization. For additional design analysis techniques, see AI Engine Stall Analysis in the Vitis IDE.
Tip: For performance measurements that reflect true
hardware throughput rather than simulation estimates, consider using the AI Engine Test Harness Performance Testing
Mode (refer to AI Engine Test Harness). Unlike
functional testing mode, it uses a pre-built DMA engine that eliminates PLIO stalls.
This allows you to validate the performance numbers obtained during simulation
against actual hardware behavior before committing to a full system build.