Memory Stalls - 2025.2 English - UG1076

AI Engine Tools and Flows User Guide (UG1076)
Document ID
UG1076
Release Date
2025-11-20
Version
2025.2 English

The objective of the mapper is to prevent buffer conflicts, where possible. The mapper has different buffer optimization levels that try to increase the size of buffers to prevent conflicts. These buffer optimization levels range from 0 (default) to 9. You can invoke them with the Xmapper option, --Xmapper=BufferOptLevel<level num>.

At the highest buffer optimization level (9), one bank cannot contain two buffers. However it is important to know that at the higher buffer optimization levels it can be impossible for the mapper to find a solution. In this case it errors out. If there are a large number of memory stalls, cycle through the BufferOptLevel options to see if fewer memory stalls are at higher bufferOptLevels.

Another possibility is to explicitly inform the mapper not to place two buffers in the same bank. You can provide a directive to the mapper to not place buffers in the same bank. This is useful if your analysis indicates a significant throughput degradation caused by memory stall resulting from a bank conflict between buffer kernel_0.in[0] and kernel_1.out[0]. Use the following.

not_equal(location<buffer>(kernel_0.in[0]), location<buffer>(kernel_1.out[0]));
Note: Buffers can be in different banks, but they might not be on the same AI Engine tile.

If DMA FIFOs are used in the design and they are placed in the same bank as other buffers then the Xrouter option DMAFIFOsInFreeBankOnly can force the router to place these FIFOs in free banks. This eliminates memory conflicts with the DMA FIFOs.

Sometimes it is not possible to reserve an entire free bank for the DMA FIFO. In this case, use location constraints in coordination with outside knowledge of memory buffers. In this case it is important to have knowledge of which buffers might cause stalls when conflicting with DMA FIFOs. The constraints can look as follows.
location<fifo>(net2) = { dma_fifo(aie_tile, 15, 0, 0x3100, 32) };