The x86 simulator uses a simplified model of the AI Engine architecture. The placement and routing of the various kernels of the AI Engine array is a simplified model. The x86 simulation does not model the routing delays and FIFO lengths.
x86 simulations compose multiple threads that share the x86 processor. As a result, the simulator does not model memory access conflicts and stream access conflicts.
When targeting the x86 simulator, the AI Engine compiler translates all vector processor specific instructions into a series of x86 instructions. Therefore, the x86 simulator does not estimate any design throughput. Furthermore, the x86 simulator does not model software pipelining.
For information about how to handle the same table definition in multiple kernels, refer to the following documents:
- For AI Engine, see Shared Graphed-Scoped Tables in the AI Engine Kernel and Graph Programming Guide (UG1079).
- For AI Engine-ML, see Shared Graphed-Scoped Tables in the AI Engine-ML Kernel and Graph Programming Guide (UG1603).