To simulate the entire system for a specific board and platform, you must use the Vitis hardware emulation flow.
This simulation includes the following:
- AI Engine graph
- PL logic along with XRT-based host application to control the AI Engine
- PL
The hardware emulation flow includes the following:
- SystemC model of the AI Engine
- Transaction-level SystemC models for the NoC, DDR memory, PL Kernels (RTL), and PS (running on QEMU)
You can also include RTL logic and test bench PL logic for your platform or design. The Application Verification Using Vitis Emulation Flow in the Data Center Acceleration using Vitis (UG1700) provides details on the flow.
For details on speed and accuracy of the system including the following:
- AI Engine
- PL models
- NoC
- DDR memory
- Other I/O models
see Speed and Accuracy of Hardware Emulation in the Embedded Design Development Using Vitis (UG1701) .
Hardware emulation only models the functional performance of PS-to-AIE communication. Tests that rely on PS-to-AIE latency, that include features such as asynchronous RTP, where PS updates are propagated asynchronously, or tests that involve PS-initiated DDR activities might be impacted by the reduced accuracy.