You can view the DMA FIFO size and stream switch FIFO size timeline in the Vitis IDE using VCD-based analysis. The IDE shows the FIFO depth that was used in the simulation. The IDE can help analyze design stall issues, and optimize the FIFO size needed. Optimizing the FIFO size helps optimize design performance.
To enable FIFO size visualization, enable the VCD dump option of
aiesimulator. You can open the simulation run result in
the IDE, for
example:aiesimulator --pkg-dir=./Work --online -wdb -text
vitis -a aiesimulator_output/default.aierun_summaryFor more options on how to run simulator and open run results, see AI Engine Stall Analysis in the Vitis IDE.
Tip: If design hangs in simulation,
use the
--simulation-cycle-timeout=<cycles>
option to stop the aiesimulator simulation at a set
time.