Files replace PL connections in AI Engine simulation and x86 simulation. You must provide the files with pre-existing data for the input. Simulation runtime creates them for the output. This can be cumbersome when a PL kernel is right in the middle of the graph. In that case, there is no direct relationship between the output values and the re-entered values on the PLIOs.
In software and hardware emulation, you must provide HLS and/or RTL code for PL located kernels. Providing this code can be a problem if the PL kernels are not yet designed.
To overcome these difficulties, you can write external traffic generators in Python, C++ or System Verilog. You can use the same traffic generator in simulation and emulation. For additional information, see Using Traffic Generators for AI Engine Designs in Embedded Design Development Using Vitis (UG1701).