Evaluating FIFO Depth To Break Deadlocks - 2025.2 English - UG1076

You can add FIFOs within the design to help with system deadlock. In a simple system, you can infer the FIFO sizes from the design and do a manual static analysis. However, you cannot know exactly how many clock cycles are spent in the main_init(), the main(), and the beginning of your kernel.

The tool computes these FIFO lengths from an AI Engine simulation for you. You can compile your graph with the AI Engine compiler using the flag --evaluate-fifo-depth. This option generates infinite FIFOs on all relevant paths.

Run a standard AI Engine simulation with aiesimulator after your code compiles. The following warning displays near the beginning of the simulation:

[CRITICAL WARNING]: Design was compiled with --evaluate-fifo-depth option, before deploying the design on hardware compile without --evaluate-fifo-depth option.

1. Open Vitis Unified IDE.
2. Open the simulation run_summary.
3. Note the Estimated FIFO column, and apply the recommended number of FIFOs using the fifo_depth constraint on specific nets.

The Estimated FIFO (Words) column provides estimated FIFO depths. You can use these values in the graph to insert FIFOs with the specified length using the following syntax:

fifo_depth(net) = value;

Where net is a connection on which you want to insert a FIFO.