The AI Engine (AIE) Test Harness provides a reference platform to run AIE applications on AMD Versal™ platforms including the VCK190 and VEK280. The Test Harness provides application designers the ease of a software simulator while conducting actual hardware testing. You can test designs for functionality and performance across diverse host systems, including x86 and Arm, using common environments like C++, Python. and MATLAB. Crucially, the test harness facilitates a simple and intuitive transition from the AIE simulation environment to hardware; you can move AIE graphs to hardware in minutes with only a few minor modifications.
The client-server architecture ensures a seamless and efficient testing experience by abstracting complexities like network communications and hardware specifics (for example, device controls). This abstraction allows you to concentrate entirely on your AIE designs. The server runs continuously on the Versal board, accepting multiple client connections over Ethernet interface on a first-come, first-served basis as shown in the preceding figure. The server processes client requests, which include initializing the device with AIE designs, running AIE graphs and DMA with client-supplied data, waiting for transaction completion, and transmitting results or AIE event traces back to the client. You can create test benches using client APIs (C++, Python, or MATLAB). This allows you to manage connections, load designs, run tests in transactions, measure performance, verify functionality, and request traces entirely from local hosts.
The AIE Test Harness supports two modes of design evaluation: functional and performance testing.
Functional Testing Mode
Functional testing mode verifies implementation correctness on hardware using large user-provided datasets transferring data between DDR and the AIE with proper buffering. Because this mode can introduce stalls due to DDR bandwidth limitations, the measured performance does not represent the graph's maximum potential throughput.
Performance Testing Mode
In contrast to functional testing mode, performance testing mode is engineered to
achieve maximum throughput on the PLIO interfaces. The DMA engine used in this mode
ensures that data transfer between the AIE and the PL is not
artificially stalled by the DMA channels, allowing for accurate performance testing
on the hardware. To accelerate development, pre-built XSA files are provided for
supported platforms. These XSAs contain necessary hardware information and the PL
DMA engine, allowing designers to skip the time-consuming v++ link
stage after compiling libadf.a. You can proceed directly to the
v++ package step to generate the final hardware boot image,
facilitating fast and predictable iteration cycles. More details about the AIE Test Harness can be found here.