Interface Ports - Interface Ports - 1.0 English - PG465

XP5IO Wizard LogiCORE IP Product Guide (PG465)
Document ID
PG465
Release Date
2025-12-03
Version
1.0 English
Table 1. Interface Ports
Port Direction Clock Domain Description
<port_name> I/O N/A Input or output ports directly connected to the package pin. The XP5IO Wizard Pin Configuration tab defines the port names. The signal name or strobe name defines the port names for each bus. Differential signals append _p or _n.
t_<port name> I N/A Combinatorial 3-state control signal for <port_name>.
data_from_fabric_<sig_name>[sf*num_pins -1:0] I   Parallel data input from the interconnect logic to TX.
  • <sig_name>: Signal name configured for TX bus direction during customization.
  • sf: Serialization factor.
  • num_pins: Number of pins associated with the signal.
fifo_rd_en I fifo_rd_clk Receiver's FIFO read clock.
fifo_rd_clk I N/A FIFO read clock for the interface.
phy_rdcs0 I   Reserved for memory controller.
phy_rdcs1 I   Reserved for memory controller.
phy_rden I   Read Enable used for RX_GATING.
phy_wrcs0 I   Reserved for memory controller.
phy_wrcs1 I   Reserved for memory controller.
phy_wren I   Read Enable used for TX_GATING and when tri-state controls are set to serialized.
pll_clkin I N/A Input clock for the PLL when you select the Include PLL in Core option.
pll_rst_in I N/A Reset connected to the PLL when you select the Include PLL in Core option.
riu_addr[87:0] I riu_clk RIU register address. 8-bits for each nibble.
riu_clk I N/A System clock to control the reset sequence. RIU_CLK must be free running.
riu_nibble_sel[10:0] I riu_clk RIU nibble select. This signal must be High to perform read/write to the nibble.
riu_rd_data[175:0] O riu_clk RIU read data from the register
riu_wr_data[175:0] I riu_clk RIU write data to the register. 16-bits for each nibble.
riu_wr_en[10:0] I riu_clk RIU write enable register (active-High).
Rst I riu_clk Reset for the reset sequence. Deassert synchronously to riu_clk.
pll_clkout0 O N/A The frequency of this is data speed divided by the serialization factor/2. You can use this clock for the general interconnect logic.
pll_clkout1 O N/A The frequency of this is data speed divided by the serialization factor/2. You can use this clock for the general interconnect logic.
pll_clkout2 O N/A The frequency of this is data speed divided by the serialization factor/2. You can use this clock as a clock for the general interconnect logic.
pll_clkoutphy O N/A When you select the Include PLL in Core option, the pll_clkoutphy port is available when multiple cores are sharing a single PLL.
pll_locked O N/A Logic High indicates the XPLL is locked to the desired clock frequency.
data_to_fabric_<sig_name>[sf*num_pins-1:0] O fifo_rd_clk, fifo_wr_clk Parallel data output to general interconnect logic from RX.
  • <sig_name>: Signal name configured for the RX bus direction during customization.
  • sf: Serialization factor.
  • num_pins: Number of pins associated with the signal.
dly_rdy O riu_clk XP5IO PHY status indicating the delay line has completed calibration.
phy_rdy O riu_clk XP5IO PHY status indicating the PHY is ready for voltage and temperature compensation (VTC).
fifo_empty O fifo_rd_clk Aggregated FIFO empty flag from each octad which contains RX/BiDir pins.
fifo_wr_clk O N/A Receiver's FIFO write clock. Reserved for future support when FIFO is set for SYNC or BYPASS operation.
gt_status I riu_clk Reserved for memory controller.
intf_rdy O riu_clk Indicates the reset sequence of the interface is done.
output wire shared_pll_clkoutphyen O riu_clk When you select the Include PLL in Core option, shared_pll_clkoutphyen is an output indicating that the reset sequence is ready to assert the PLL's CLKOUTPHYEN. Use this output with another core sharing the PLL (Include PLL in Core option not selected). See the example design.
rxtx_cntvaluein_<sig_name>[9*num_pins -1 : 0] I riu_clk The CNTVALUEIN pins dynamically switch the loadable tap value. The CNTVALUEIN is the number of taps required. The new value is best applied one clock cycle before applying the LOAD signal. The delay line can change from 1 to 8 taps at a time.
rxtx_cntvalueout_<sig_name>[9*num_pins -1 : 0] O riu_clk The CNTVALUEOUT pins report the current tap value and read out the amount of taps in the current delay. When EN_VTC is High, the IDELAYCTRL updates CNTVALUEOUT.
rxen_vtc_<sig_name>[num_pins -1 : 0] I riu_clk Enable voltage, temperature, and process calibration/compensation.
  • High: Allows XP5IO to keep delay constant over VT. EN_VTC must be HIGH for VT compensation to be enabled.
  • Low: VT compensation is disabled.

When using TIME mode, the RX_EN_VTC signal must pull High during the initial built-in self-calibration (BISC). When using COUNT mode, the RX_EN_VTC signal must pull Low. When using bit slices in both TIME and COUNT mode in a nibble, RX_EN_VTC must pull High for the bit slices used in TIME mode, and must pull Low for those in COUNT mode.
rxtxen_ce_<sig_name>[num_pins -1 : 0] I riu_clk Clock enable for the delay line register lock.
rxtx_inc_<sig_name>[num_pins -1 : 0] I riu_clk The increment/decrement is controlled by the enable signal (RX_CE). This interface is only available when the delay line is in VARIABLE or VAR_LOAD mode. As long as CE remains High, the delay line increments or decrements by one tap every clock (RX_CLK) cycle. The state of RX_INC determines whether the delay line increments or decrement, synchronously to the clock (RX_CLK)s:
  • RX_INC = 1 increments
  • RX_INC = 0 decrements

If RX_CE is Low, the delay through the delay line does not change (regardless of the state of RX_INC). The programmable delay taps in the delay line wraps around. When the last tap delay is reached (RX_CNTVALUEOUT = 511), a subsequent increment function returns to tap 0. The same applies to the decrement function: decrementing from zero moves to tap 511.
rxtx_ld_<sig_name>[num_pins -1 : 0] I riu_clk When in VAR_LOAD mode and RX_UPDATE_MODE=ASYNC, the delay line load port, RX_LOAD, loads the value set by the RX_CNTVALUEIN into the delay line. The value present at RX_CNTVALUEIN[8:0] is the new tap value. The RX_LOAD signal is an active-High signal and is synchronous to the input clock signal (RX_CLK). Wait at least one RX_CLK clock cycle after applying a new value on the RX_CNTVALUEIN bus before applying the LOAD signal. RX_CE must be held Low during RX_LOAD operation.
rxtx_sel_<sig_name>[num_pins -1 : 0] I riu_clk  
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