General Design Guidelines - General Design Guidelines - 1.0 English - PG465

XP5IO Wizard LogiCORE IP Product Guide (PG465)

Document ID
PG465
Release Date
2025-12-03
Version
1.0 English

You can configure the XP5IO Wizard over a wide range of interface speeds for source synchronous configurations. You are expected to have the interface requirements of your application before generating the XP5IO Wizard specific to your designs, such as interface speed, clock to data relationship, and system clocking structure. For example, what the source of the XPLL input clock must be.

After the wizard generates the HDL wrapper, runs synthesis, and performs pin planning using the Advanced I/O Planner tools. For more information, see Using the Advanced I/O Planner.