The XP5IO Wizard core provides the source HDL wrapper for the high-performance XP5IO. It also generates the optimum pin placement for the user-defined interface pins. The wizard configures the bus direction, clock to data alignment, interface speed, PLL clock source, and PLLE4XP input clock frequency.
For the example design, the XP5IO Wizard provides constraints based on the I/O standard and DC bias selections.
The wizard builds a complex high speed I/O interface through parameter settings, clock setup, clock routing, and forwarding that allows simple I/O user input for complex applications.
The wizard configures pin/bus selection, bus direction, signal type, data/strobe, and signal name. It allows you to choose the TX/RX/RX + TX bus direction for the signals in the interface. Each I/O bank contains up to 64 pins that you can configure as TX or RX. The wizard provides the following features:
- TX/RX
- Single Ended/Differential I/O
- Data/Strobe/Input Clock/Clock Forward
- Optional customizable bus signal name
- Shim flop to optimize fabric performance