For XP5IO PHYs, the PLL (PLLE4XP_ADV) is recommended to be part of the wizard. The calibration algorithms and clock buffers are critical to the XP5IO calibration process which requires the wizard to have access to all of the PLL ports and primitives.
For every two banks, the XP5IO interfaces must use one of the two PLLs which are shared across the two banks. For example, an interface in bank 704 must use a PLL from either bank 704 or bank 705. Similarly, an interface in bank 707 must use an PLL from bank 706 or bank 707.
The input clock for the PLL is configured by the Clocking section to achieve a given data rate and is based on the RX and TX Serialization Factors.
For TX interfaces, the parallel data is clocked by the following PLL. The destination clock used for timing is provided as an output connection. For the port names, see the instantiation template.
For RX interfaces, the parallel data for the receive interface read out by
the clock connected to the fifo_rd_clk input port within the
instantiation template. The PLL output clocks are available in the instantiation template.
For advanced customers using the FIFO_WR_CLK, an additional clock constraint
must be applied to the strobe/rdClk input.