Basic Tab - Basic Tab - 1.0 English - PG465

Component Name

User defined. Name must not contain any reserved Verilog words.

Application

Source Synchronous

Indicates that the data’s capture clock is presented along with the serialized data.

Bus Direction

TX ONLY

Indicates that the user design contains only TX pins.

RX ONLY

Indicates that the user design contains only RX pins.

Clocking

Interface Speed

Serial data-rate in Mb/s.

PLL Clock Source

Fabric (Driven by BUFG)

Choose this option if the clock is sent by clocking. A clock buffer, such as a BUFGCE, might be needed. Not all clock buffers can drive the PLL.

Clock Capable Pin

Reserved for future use

PLL Input Clock Frequency

Input clock frequency. Allowable input frequencies depend on the interface speed and allowable PLL settings. The core shows the allowable frequencies.

Forward Clock Phase

0

The CLK_FWD pin (Signal Type = CLK_FWD) transmits edge aligned to data.

90

The CLK_FWD pin (Signal Type = CLK_FWD) transmits center aligned to data.

Data and Control

TX/RX Serialization Factor

Defines the serialization factor and parallel data input/output from the general interconnect. Legal values are 2, 4, 8, or 16.

3-State

Combinatorial

Uses T pin of the X5PHIO_LS from the general interconnect logic to control the 3-state of the TX and BiDir pins.

Serialized

Uses PHY_WREN to serialize the 3-state of the TX and BiDir pins. Reserved for future use.

Include PLL in Core

When selected, the core instantiates PLL; otherwise, reserved for future use.