Figure 1. Advanced Tab
- Optional Ports
-
- PLL CLKOUT1
- Unused PLL_CLKOUT1 optionally available.
- FIFO_WRCLK_OUT
- Reserved for future use. Typically used when FIFO_MODE set to SYNC or BYPASS. Timing calculations require the strobe pin to have a clock constraint to generate the correct FIFO_WRCLK frequency. For example, if an interface is running at 1000 Mb/s, then the strobe frequency needs to be 500 MHz because XP5IO uses a DDR strobe.
- REDUCE CONTROL SIGNALS
- Reserved for future use.
- ENABLE ALL PORTS of XPHY
- Adds all XP5IO controls signals for advanced applications.
- ENABLE DELAY CONTROL SIGNALS
- Adds the delay control signals (
rxen_vtc,rxtx_ce,rxtx_cntvaluein,rxtx_inc,rxtx_ld,rxtx_sel,cntvaluein,cntvalueout). - Enable shim flop logic
- Improve clock speeds for PL logic interfaces. A flop internal to the memory controller is enabled for XP5IO interfaces.
- Advanced Clocking
-
- Generate RIU Clock from PLL
- Reserved for future use.
- Debug
-
- Generate RIU Clock from PLL
- Reserved for future use.
- IO Standard Selection
-
- Differential IO Std
- Sets the differential IO Standard for the example design.
- Single IO Std
- Sets the single ended IO Standard for the example design.
- Differential IO Std
-
- FIFO_WRCLK_OUT
- Reserved for future use. Typically used when FIFO_MODE set to SYNC or BYPASS. Timing calculations require the strobe pin to have a clock constraint to generate the correct FIFO_WRCLK frequency. For example, if an interface is running at 1000 Mb/s, then the strobe frequency needs to be 500 MHz because XP5IO uses a DDR strobe.
- REDUCE CONTROL SIGNALS
- Reserved for future use.
- ENABLE ALL PORTS of XPHY
- Adds all XP5IO controls signals for advanced applications.
- ENABLE DELAY CONTROL SIGNALS
- Adds the delay control signals
(
rxen_vtc,rxtx_ce,rxtx_cntvaluein,rxtx_inc,rxtx_ld,rxtx_sel,cntvaluein,cntvalueout).
- Number of Banks
- Reserved for future use.