XTS-AES-256 Encryption and Decryption - XTS-AES-256 Encryption and Decryption - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

XTS-AES-256 (XEX Tweakable Block Cipher with Ciphertext Stealing, defined in IEEE Std 1619) is a symmetric encryption algorithm specifically designed for storage and memory encryption. It provides strong data confidentiality while efficiently handling the fixed-address-based structure of DRAM systems.

XTS-AES-256 is recommended when the following applies:

  • The protected region is large (hundreds of MB or more).
  • Maximum memory bandwidth must be preserved.
  • Data integrity verification (authentication) is not required.
  • No DRAM capacity overhead for metadata is acceptable.