What is an X5IO Bank?
Each DDRMC5 interface uses pins from dedicated high-speed X5IO banks designed for memory interfaces. On Gen 2 devices, these banks are numbered starting from 700 (for example, 700, 701, 702, ..., 715). The exact number of banks depends on the device.
DDRMC5X uses two consecutive X5IO banks. DDRMC5C/E configurations span three consecutive banks, although the third bank can be partially bonded out depending on the device/package combination.
How Pins Are Named
Every pin in an X5IO bank has a structured name that tells you exactly where it sits in the bank hierarchy. Following is an example.
IO_L1P_XCC_H0O0P2_M0P2_700
Reading from left to right:
| Part | Meaning |
|---|---|
| `IO_L1P` | Lane pair 1, Positive side (`P` = true, `N` = complement) |
| `XCC` | This pin is clock-capable (can carry strobe/clock signals) |
| `H0` | Located in Half Bank 0 |
| `O0` | Located in Octad 0 (group of 8 pins) |
| `P2` | Position 2 within the octad |
| `M0` | Belongs to Memory Controller 0 |
| `P2` | Is pin 2 of the 96-pin controller interface |
| `700` | In Bank 700 |