In this stage the write DQS to DQ centering is done with a complex pattern. In the Write DQ complex calibration, bursts of complex pattern are written into the DRAM device and read back by a dedicated complex hard logic. The read data is compared by the hard logic and updates a ODS register with comparison status. The comparisons are bitwise separate for rising and falling clock edges. Based on the comparison result the write path delay of the DQ lines are changed to center align with respect to the DQS.