Not all pins within an octad are equal. A pin's position within the octad determines the signal type it can carry. Refer to the following table.
| Position | Pin Type | Supported Signals |
|---|---|---|
| P0, P1, P4, P5 | General purpose | DQ data bits, CA command/address, CS chip select |
| P2, P3 | XCC (clock-capable) | DQS/RDQS strobes, WCK write clocks, CK memory clocks, DM data masks |
| P6, P7 | GC (global clock). Octad 0 only | System reference clock input, CS chip select. GC capability exists only on P6/P7 of Octad 0 in each bank. In data byte regions these pins are typically unused. In control regions they can carry CS, CA, or reset signals |
Important: All clocked signals (strobes, write clocks,
memory clocks) must be placed on XCC positions (P2/P3). The
DDRMC5 controller enforces this automatically, so you do not need to manage it
manually.