DDRMC5X uses two consecutive X5IO banks. DDRMC5C/E configurations span three consecutive banks, although the third bank can be partially bonded out depending on the device/package combination. Refer to the following table.
| Bank Position | Controller Pin Range | |
|---|---|---|
| First bank | M*P0 through M*P31 | 32 |
| Second Bank | M*P32 through M*P63 | 32 |
| Third Bank | M*P64 through M*P95 | 32 |
The **M\*P\* number** is the controller's internal
pin index. It stays the same regardless of which physical bank the pin is in. For
example, DQ[0] always maps to the same M*P* position whether the
DDRMC is on banks 700-702 or banks 706-708.
Controller pins M\*P0 through M\*P95 map
sequentially across three banks.
Figure 1. DDRMC5 Normal Orientation
