The Pin Hierarchy: Banks → Octads → Pins - The Pin Hierarchy: Banks → Octads → Pins - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

Use the following analogy to understand the bank structure.

Think of the bank structure like a street address. A bank is like a neighborhood, an octad is like a block, and each pin has a house number.

Bank 700 (32 pins)
│
├── Octad 0  (8 pins)
│   ├── P0  IO_L0P  ── General purpose (data, CA, CS)
│   ├── P1  IO_L0N  ── General purpose
│   ├── P2  IO_L1P  ── ★ XCC: Clock-capable (strobes, clocks, DM)
│   ├── P3  IO_L1N  ── ★ XCC: Clock-capable
│   ├── P4  IO_L2P  ── General purpose
│   ├── P5  IO_L2N  ── General purpose
│   ├── P6  IO_L3P  ── ★ GC: Global clock input
│   └── P7  IO_L3N  ── ★ GC: Global clock input
│
├── Octad 1  (8 pins, XCC on P2/P3, P6/P7 are general purpose)
├── Octad 2  (8 pins, XCC on P2/P3, P6/P7 are general purpose)
└── Octad 3  (8 pins, XCC on P2/P3, P6/P7 are general purpose)

Every bank has exactly 4 octads × 8 pins = 32 I/O pins (plus power and reference voltage pins).

Each bank contains four octads of eight pins. Clock-capable (XCC) positions P2/P3 are required for strobe and clock signals.

Figure 1. X5IO Bank Structure