Supported DIMM Topologies and Known Limitations - Supported DIMM Topologies and Known Limitations - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

The following table shows topologies supported for DDR5 RDIMM and CUDIMM/CSODIMM interfaces.

Table 1. Supported RDIMM/CUDIMM Topologies
Topology Notes
Single memory controller + single RDIMM slot Supported
Single memory controller + dual RDIMM slots Both DIMMs must use unique HID values.
Multiple memory controllers, each with RDIMM All DIMM slots share the single PMC I2C bus. Each slot must have a unique HID.
Single MC + RDIMM + CUDIMM/CSODIMM mixed RDIMM and CUDIMM/CSODIMM HID values must all be unique across the shared PMC I2C bus.
Note: Slot-0 is the DIMM slot farthest from the Versal device on the PCB and corresponds to rank-0 and rank-1. Slot-1 is the near slot. Label slots clearly on the PCB silkscreen to avoid HSA resistor assignment errors.