Step 3: Generating Final PDIs with the ACE Overlay CDO - Step 3: Generating Final PDIs with the ACE Overlay CDO - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English
Perform the following steps after all the controllers are configured in ACE:
  1. Click Save. The isolation specification file (isospec.iss) generates.
  2. Click Write CDO. The overlay CDO file (overlay.cdo) generates. This contains all ILECC and Crypto configuration data to merge into the device PDI.
  3. Click Exit.
  4. Close the browser.
  5. Run bootgen to merge the overlay CDO into the Vivado-generated PDIs:
    cd project_1.runs/impl_1/
bootgen -arch versal_2ve_2vm \
        -image design_1_wrapper_boot.bif -w \
        -o design_1_wrapper_boot_final.pdi
bootgen -arch versal_2ve_2vm \
        -image design_1_wrapper_pld.bif  -w \
        -o design_1_wrapper_pld_final.pdi
    Note: The -arch versal_2ve_2vm string applies to Versal AI Edge Series Gen 2. Verify the correct arch string for your target device family in the bootgen documentation before running these commands.
  6. Download design_1_wrapper_boot_final.pdi and design_1_wrapper_pld_final.pdi to hardware using Vivado Hardware Manager. Do not use the intermediate Vivado-generated PDIs for hardware bring-up when ILECC or Crypto is enabled