Step 1: Enabling Inline ECC and Crypto in the Vivado IP GUI - Step 1: Enabling Inline ECC and Crypto in the Vivado IP GUI - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English
  1. Double-click the AXI NoC2 IP configuration dialog box.
  2. Navigate to the DDRMC5 Configuration tab.
  3. Click Configure DDRMC5.
    Table 1. DDRMC5 Configuration Options
    GUI Control Action
    Inline ECC check box Check to enable the ILC block and ECC interleaving hardware. You must enable ILECC here before configuration in ACE.
    Crypto drop-down
    None
    No encryption (default).
    XTS
    Enable XTS-AES-256 hardware block.
    GCM
    Enable AES-GCM-256 hardware block.
    XTS GCM
    Enable both; region type assigned per region in ACE.
    Note: These GUI selections determine which hardware logic is generated in the device image. They do not configure the actual memory regions or key parameters—ACE performs that after implementation.
  4. Complete the Vivado design flow. Click create HDL Wrapper > add board XDC constraints > Generate Device Image > export XSA (with Include device image selected).