Revision History - Revision History - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)
Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

The following table shows the revision history for this document.

Section Revision Summary
08/07/2026 Version 1.0
Inline Encryption (Crypto) New section.
Memory Controller Pinout Rules Section rewritten.
DDR5 PMIC I2C/I3C Interface New section.
Pinout Options Clarified and updated pinout options for LP5 and LPDDR5
DDR5 Pinouts for Supported Configurations Updated figures with notes.
DDR5 Pin Rules Updated figures.
General updates CSODIMM Support.
Differences between DDRMC5C, DDRMC5E, and DDRMC5X Section updated.
Memory Configuration Support Removed density statement.
Memory Controller Architecture Content restructure.
Designing with the Core
  • Content restructure.
  • Section rewrite.
Memory Controller Pinout Rules Content restructure/rewrite.
01/08/2026 Version 1.0
General updates Clarification around half bank wording throughout.
DDR5 PMIC I2C/I3C Interface New section.
Memory Controller Feature Summary
  • Added RDIMM and CUDIMM support.
  • Updated note.
  • Updated supported topologies.
  • New bullet for LPDDR5/5X Bank Architecture.
  • Clarified AES-XTS Encryption.
Memory Controller Simulation
  • Clarified performance analysis information relating to hardware.
  • Updated list of minimal impact items.
Reordering WAW/RAW content added.
Differences between DDRMC5C, DDRMC5E, and DDRMC5X Updated tables and text for DDRMC5X support.
Memory Controller Pinout Rules Rewrite of figure introduction text.
Packed to the Left v Packed to the Right Added note for memory controller orientation.
06/03/2025 Version 1.0
Initial AMD release. This document (PG456) originated from the division of DDRMC content previously contained in PG406.