The Memory Controller uses a state machine to determine reordering priority. Depending on the state of the transactions, it either optimizes for efficiency (reordering to take advantage of open pages) or it can service transactions which have been left idle for too long.
Generally, the memory controller reorders transactions to maximize page hits, bank interleave, and to minimize bus turnarounds from reads to writes, and vice versa. Per-transaction timers are maintained for all outstanding transactions. If transactions have gone unserviced for too long, priority is shifted. Counters also monitor for starvation to make sure transactions are not stalled.
The memory controller also checks for write-after-write (WAW) and read-after-write (RAW). A WAW occurs when two write requests to the same address enter the controller command queue before the first write has been sent to the DRAM. In this case, the second write replaces the first write, and only one write command is executed. A RAW occurs when a read request matches the address of an outstanding write request in the command queue. In this case, a separate read command is entered into the command queue, but as soon as the write is executed, the read is bypassed, and the write data is directly returned to the read requester. This combining of transactions can make the overall bandwidth appear to exceed the maximum DRAM bandwidth.