Read DQ Calibration is required to center the PDQS (rising edge) and NDQS (falling edge) clocks to the valid region of data. The read path data is sampled on the read DQS strobe generated by memory, which is aligned with read data.
Before sampling read data the DQS strobe passes through the gate logic. The gate logic drives gated PDQS and NDQS out of the input DQS strobe. These PDQS and NDQS signals go via per bitslice pqtr and per bitslice nqtr delay taps respectively and become input clocks to the per bitslice de-serializer logic. The read data comes directly to the de-serializer logic. The PDQS and NDQS sample alternate edges of data one after another. In order to properly sample the read data with enough setup and hold time the PDQS and NDQS clocks are centered to the valid region by the per bitslice pqtr/nqtr taps.