The PCAMP/CAMP pin on an RDIMM defaults to PWR_GOOD
output functionality. It is driven by the on-DIMM PMIC to indicate that all DIMM
power rails have reached their target voltages.
- Power sequencing
-
PWR_GOOD(PCAMP asserted) must occur before Versal POR is released to the memory subsystem. This must be ensured at the board level. - FPGA connection
- The Versal DDRMC5 or firmware does not monitor PCAMP. Memory controller operation does not require tie-off or FPGA GPIO connection. On many board designs, PCAMP is connected to an LED for visual indication.
References
- JESD301-1
- JESD301-3
- JESD301-4
- JESD301-5