Quick-Reference Checklist - Quick-Reference Checklist - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

Use the following checklist for any new design that requires inline ECC or inline encryption.

Table 1. Checklist
# Action Tool
1 Enable Inline ECC check box and/or Crypto drop-down in the AXI NoC2 IP GUI, DDRMC5 Configuration tab. Vivado
2 Complete HDL Wrapper → add board XDC constraints → Generate Device Image. Vivado
3 Export Hardware (XSA) with “Include device image” selected. Vivado
4 Launch ACE: ace --xsa <file>.xsa --gui. ACE
5 For each ILECC controller: check Inline ECC; verify ACE partition calculations (Max ECC Protected, ECC Storage, Available Memory). ACE
6 For each XTS controller: Enable XMPU; add Subsystems access row with Encryption = xts; set SMIDs to ANY. ACE
7 For each GCM controller: Enable XMPU; set Reserved GCM Data Size; optionally enable Second Auth / Countermeasures / Inline ECC; add Destination; add Subsystems row with Encryption = gcm; set SMIDs to ANY. ACE
8 Save (.iss) → Write CDO (.cdo) → Exit ACE
9 Run bootgen with BIF files + overlay CDO to generate final PDIs. bootgen
10 Program hardware with boot_final.pdi and pld_final.pdi. Hardware Manager
11 Verify using xsdb and NoC performance monitors; confirm ECC and Crypto ISR registers are clean. xsdb