The Memory Controller will periodically issue a read instruction to the DRAM to ensure that read clocks are returned for DQS/RDQS gate tracking purposes. During calibration the DQS/RDQS are aligned with an internal clock, and this alignment is adjusted during normal operation. In order for this adjustment to occur, a read DQS/RDQS is required. An internal counter keeps track of the time elapsed since a read DQS/RDQS has arrived, and if one has not arrived in the last 20 μs, the controller will insert a 'dummy read' solely for the purpose of receiving the DQS/RDQS for tracking. The data returned from the DRAM is discarded at the PHY and is not returned to the memory controller.
Memory access patterns with long continuous writes have a small efficiency impact as a read operation creates a read-write turnaround delay. If the memory access contains a mix of read and write commands, provided two reads are within 20 μs of each other, the controller does not need to insert any periodic reads.