The Versal architecture PHY is composed of dedicated blocks and integrated calibration logic. The dedicated blocks are structured adjacent to one another with back-to-back interconnects to minimize the clock and datapath routing necessary to build high performance physical layers. The Memory Controller and calibration logic communicate with this dedicated PHY in the slow frequency clock domain, which is either one fourth or equal to the DRAM clock frequency. This depends on the DDR5 or LPDDR5/5X memory clock.