Overview - Overview - 1.0 English - PG456

Integrated DDR5/LPDDR5/5X Memory Controller LogiCORE IP Product Guide (PG456)

Document_ID
PG456
Release_Date
2026-08-07
Version
1.0 English

When you configure a DDRMC5 memory interface in a design, the Vivado tools assign your DDR signals (data, strobes, clocks, command/address) to specific package pins. This section explains how those pins are organized, how to read the pinout file, and why the same memory configuration can look different on different DDRMCs.