IP Facts
Overview
Introduction
Memory Controller Feature Summary
Differences between DDRMC5C, DDRMC5E, and DDRMC5X
Memory Configuration Support
Clocking
Reset
Memory Controller Simulation
DDRMC5 Responder Core
DDR5 PMIC I2C/I3C Interface
DDR5 RDIMM and Clock Unbuffered DIMM I2C Interface
Supported DDR5 DIMM Types
I2C Interface Overview
I2C Communication Scope per DIMM Type
Host Sideband Signals (HSA, HSCL, HSDA)
Host SidebandBus Address
HSCL and HSDA—Voltage and Pull-up Requirements
I2C Device Addressing Model
Address Composition
Addressing Example—Two-RDIMM Design
Multi-DIMM Addressing Rules
Supported DIMM Topologies and Known Limitations
DDRMC5 Wizard Configuration: HID Value Assignment
Wizard Field Labels
Default HID Values
Design Rule Check Enforcement
CUDIMM/CSODIMM-Specific I2C Behavior
SODIMM and CSODIMM Considerations
Power Management Signals
RDIMM—PCAMP (CAMP/PWR_GOOD) Pin
UDIMM/SODIMM—PWR_EN and PWR_GOOD
PMC MIO Pin Assignment for I2C
Memory Controller Architecture
Core Architecture
Reordering
Auto-Precharge
ECC
ECC Scrubbing
Address Parity
Address Parity Error Injection
Periodic Reads
Refresh
DRAM Power Down and Self-Refresh
PHY
PHY Architecture
Inline Encryption (Crypto)
XTS-AES-256 Encryption and Decryption
AES-GCM-256 Encryption, Decryption, and Authentication
DPA Countermeasures
Effects of enabling DPA Countermeasures:
Memory Protection Regions (XMPU Configuration)
Key Rolling
AES-GCM-256 Specifics and Memory Partitioning
GCM-Specific Options
Performance and Capacity Summary
Inline Encryption Restrictions
Configuring Inline ECC and Encryption Using the Advanced Configuration Editor
Two-Step Configuration Workflow
Step 1: Enabling Inline ECC and Crypto in the Vivado IP GUI
Step 2: Configuring ILECC and Crypto in the Advanced Configuration Editor
Configuring Inline ECC (per ILECC controller)
Configuring XTS-AES-256 (per XTS controller)
Configuring AES-GCM-256 (per GCM Controller)
Step 3: Generating Final PDIs with the ACE Overlay CDO
Quick-Reference Checklist
System Design Considerations
DDR5 Component Choice
Multi-Rank DRAM Configurations
Memory Interleaving
Short Transactions: Read vs. Write
Transaction Size
LPDDR5/5X Refresh Options
DRAM Addressing
DRAM Address Mapping
Address Mapping Notation
Examples of Traffic Patterns and Choice of Mapping
Single-Thread Linear Read
Multi-Thread Linear Read/Write
Random Addressing
Designing with the Core
Configuring the DDRMC5 Memory Controller via the AXI NoC2 IP
AXI NoC2 IP Customization—General Tab
Memory Controllers - DDR5/LPDDR5
AXI NoC2 IP Customization—DDRMC5 Configuration Tab
DDRMC5 Configuration Dialog Box
DDR Basic Tab
Controller Selection
Clocking
DDR Memory Options Tab
Device Type
Speed Bin
Base Component Width
Memory Density Parameters
Physical Interface
Operating Temperature
Mode Register Settings
Address Map Options Tab
Pre Defined Address Map
User Defined Address Map
DDR Advanced Tab
Refresh Options
ECC Options
Startup Options
DDR5 Controller Options
Startup Options
Memory Controller Pinout Rules
Overview
X5IO Bank Architecture
The Pin Hierarchy: Banks → Octads → Pins
Which Pins Can Carry Which Signals?
Three Banks Per DDRMC
Normal versus Flipped DDRMC Orientation
Why Do DDRMCs Look Different?
Normal Orientation
Flipped (Mirrored) Orientation
Side-by-Side Comparison
Determine Whether the DDRMC Is Normal or Flipped
Packed to the Left versus Packed to the Right
What Does Packing Control?
Packed to the Right
Packed to the Left
Why the Same Configuration Looks Different on Normal versus Flipped
Bank Availability and Supported Configurations
DDRMC5 Controller Types and Associated Banks
Configurations Supported with Two Banks
Configurations Supported with Two Banks Plus Partial Third Bank
Configurations Supported with Three Full Banks
Reading the Pinout CSV File
Exporting the Pinout CSV File
Analyzing the Pinout
Matching the CSV to the Package Pins View
Pinout Options
LPDDR5/5X Pinout Options
2x16 (Dual Channel, 2 CA) — Options: Optimum, Packed Left, Packed Right
1x16 (Single Channel, 1 CA) — Options: Packed Left, Packed Right, Channel Expansion
1x32 (Single Channel, 1 CA) — Options: Packed Left, Packed Right, Packed Right with Optimum
DDR5 Component Pinout Options
DDR5 x4 Component (x16/x20 Data Width)
DDR5 x8/x16 Component (x16 to x40 Data Width)
DDR5 DIMM Pinout Options
DDR5
DDR5 Pin Rules
DDR5 Pinouts for Supported Configurations
DDR5 (x8) Pinout for 80-bit 2 Rank RDIMM Interfaces
DDR5 (x4) Pinout for 80-bit 2 Rank RDIMM Interfaces
DDR5 (x8) Pinout for 72-bit 2 Rank UDIMM/SODIMM/CUDIMM Interfaces
Component Interface Pinout Diagrams
Connectivity Requirements
Restrictions
Reference
LPDDR5/5X
LPDDR5/5X Pin Rules
LPDDR5/5X Pinout for Supported Configurations
LPDDR5/5X Pinout for Component Interfaces
1x32, 2 Rank, 1 CA Component Interface
2x16, 2 Rank, 2 CA Component Interface
1x16, 2 Rank, 1 CA Component Interface
Memory Interface Debug
General Memory Debug Checklist
Vivado Hardware Manager – Memory Debug
Memory Debug: GUI Usage
Memory Debug: Tcl Usage
Calibration Error Codes
DDRMC Calibration Debug
LPDDR5/5X Calibration Stages
DDR5 Calibration Stages (RDIMM and Component/UDIMM)
PHY BISC
Memory Initialization and Configuration
CS/CA Calibration
RCD CS/CA Calibration (DDR5)
Write Leveling (External)
Write Leveling (Internal) (DDR5)
DQS Gate
Write DQS (WCK) Duty Cycle Training
VREF Calibration
Read DQ Simple
Write DQ/DM Simple
Read DBI (Simple)
Read DQS-DQ/DBI Centering Complex
Write DQS-DQ/DM Centering Complex
Sanity Check: Write-Read
Mission Mode Tracking
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices
Maximum devices
Maximum of eight DIMM slots per PMC I2C Master bus (HID values
0x0–0x7).
Cross-controller uniqueness
All RDIMM slots and CUDIMM/CSODIMM slots on all memory controllers share the
single PMC I2C bus. RDIMM HID values and CUDIMM/CSODIMM HID values must all
be unique across the entire design — even across different controllers.
CUDIMM/CSODIMM + RDIMM mixed
CUDIMM/CSODIMM and RDIMMs must have different HID values (different lower
three bits) when sharing the same PMC I2C bus.